Silicon carbide semiconductor device

ABSTRACT

A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration N A . A relaxation region is provided in a portion of the second surface of the first drift layer. The first drift layer and the second drift layer form a drift region in which the relaxation region is buried. The second drift layer has an impurity concentration N B , N B &gt;N A  being satisfied. A body region, a source region, and a second electrode are provided on the second drift layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a silicon carbide semiconductor device,in particular, a silicon carbide semiconductor device having a driftregion.

2. Description of the Background Art

Regarding a Si (silicon) MOSFET (Metal Oxide Semiconductor Field EffectTransistor), which is a pervasive power semiconductor device, a maindetermination factor for breakdown voltage is the upper limit ofelectric field strength with which a drift layer serving as a breakdownvoltage holding region can withstand. Such a drift layer formed of Sican be broken at a portion fed with an electric field of approximately0.3 MV/cm or more. Hence, it is necessary to suppress the electric fieldstrength to less than a predetermined value in the whole of the driftlayer of the MOSFET. The simplest method to suppress is to decrease animpurity concentration of the drift layer. However, with this method,the on-resistance of the MOSFET becomes large, disadvantageously. Inother words, there is a trade-off relation between the on-resistance andthe breakdown voltage.

Japanese Patent Laying-Open No. 9-191109 describes such a trade-offrelation between the on-resistance and the breakdown voltage in atypical Si MOSFET while considering a theoretical limit resulting from aproperty value of Si. In order to overcome this trade off, it isdisclosed to add a lower p type buried layer and an upper p type buriedlayer in an n base layer disposed on an n type substrate disposed on adrain electrode. By the lower p type buried layer and the upper buriedlayer, the n base layer is divided into a lower stage, a middle stage,and an upper stage, each of which has the same thickness. According toone embodiment described in this patent publication, when an appliedvoltage reaches 200 V, punch through first occurs in the upper stage.Further, when the applied voltage reaches 400 V, punch through occurs inthe middle stage. Furthermore, when the applied voltage reaches 600 V,punch through occurs in the lower stage. The stages in each of which thepunch through has occurred hold equal voltages and the maximum electricfield of each stage is maintained to be equal to or less than a limitelectric field strength.

In order to further improve the above-described trade off, in recentyears, it has been actively discussed to use SiC (silicon carbide)instead of Si. Unlike Si, SiC is a material capable of sufficientlywithstanding an electric field strength of not less than 0.4 MV/cm.

A problem arising under application of such a high electric field isbreakdown resulting from concentrated electric fields at a specificlocation in the MOSFET structure. For example, in the case of a trenchtype MOSFET, a main determination factor for breakdown voltage is abreakdown phenomenon of a gate insulating film. The breakdown phenomenonoccurs at a bottom portion of the trench, in particular, a cornerportion thereof, due to concentrated electric fields in the gateinsulating film. Thus, the determination factor for breakdown voltage inthe Si semiconductor device and the determination factor for breakdownvoltage in the SiC semiconductor device are different from each other.Hence, if the technique of the above-described patent publication, whichpresumably assumes use of Si, is simply applied to improve the breakdownvoltage of the SiC semiconductor device, the breakdown voltage cannot beimproved by sufficiently using advantages in physical properties of SiC.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problem andhas its object to provide a silicon carbide semiconductor device havinga high breakdown voltage and a low on-resistance.

A silicon carbide semiconductor device of the present invention includesa first electrode, a first drift layer, a relaxation region, a seconddrift layer, a body region, a source region, a second electrode, a gateinsulating film, and a gate electrode. The first drift layer has a firstsurface facing the first electrode and electrically connected to thefirst electrode and a second surface opposite to the first surface. Thefirst drift layer has first conductivity type, and has an impurityconcentration N_(A). The relaxation region is provided in a portion ofthe second surface of the first drift layer, and has a distance L_(A)from the first surface. The relaxation region has second conductivitytype. The second drift layer has a third surface in contact with thesecond surface and a fourth surface opposite to the third surface. Thesecond drift layer has the first conductivity type. The first driftlayer and the second drift layer form a drift region in which therelaxation region is buried. The second drift layer has an impurityconcentration N_(B), N_(B)>N_(A) being satisfied. The body region isprovided on the fourth surface of the second drift layer. The bodyregion has the second conductivity type. The source region is providedon the body region, and is separated from the drift region by the bodyregion. The source region has the first conductivity type. The secondelectrode is electrically connected to the source region. The gateinsulating film includes a portion on the body region to connect thesource region and the second drift layer to each other. The gateelectrode is provided on the gate insulating film.

According to the present invention, there is obtained a silicon carbidesemiconductor device having a high breakdown voltage and a lowon-resistance.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial cross sectional view schematically showing aconfiguration of a silicon carbide semiconductor device in a firstembodiment of the present invention.

FIG. 2 is a partial perspective view schematically showing a shape of asilicon carbide layer provided in the silicon carbide semiconductordevice of FIG. 1.

FIG. 3 is a partial top view schematically showing the shape of thesilicon carbide layer provided in the silicon carbide semiconductordevice of FIG. 1.

FIG. 4 is a partial cross sectional view schematically showing a firststep in a method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 5 is a partial cross sectional view schematically showing a secondstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 6 is a partial cross sectional view schematically showing a thirdstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 7 is a partial cross sectional view schematically showing a fourthstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 8 is a partial cross sectional view schematically showing a fifthstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 9 is a partial cross sectional view schematically showing a sixthstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 10 is a partial cross sectional view schematically showing aseventh step of the method of manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 11 is a partial cross sectional view schematically showing aneighth step of the method of manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 12 is a partial cross sectional view schematically showing a ninthstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 13 is a partial cross sectional view schematically showing a tenthstep of the method of manufacturing the silicon carbide semiconductordevice of FIG. 1.

FIG. 14 is a partial cross sectional view schematically showing aneleventh step of the method of manufacturing the silicon carbidesemiconductor device of FIG. 1.

FIG. 15 is a partial cross sectional view schematically showing a finestructure of a surface of the silicon carbide layer provided in thesilicon carbide semiconductor device.

FIG. 16 shows a crystal structure of a (000-1) plane in a hexagonalcrystal of polytype 4H.

FIG. 17 shows a crystal structure of a (11-20) plane along a lineXVII-XVII in FIG. 16.

FIG. 18 shows a crystal structure of a combined plane of FIG. 15 withinthe (11-20) plane in the vicinity of the surface.

FIG. 19 shows the combined plane of FIG. 15 when viewed from the (01-10)plane.

FIG. 20 is a graph showing an exemplary relation between channelmobility and an angle between a channel surface and the (000-1) planewhen macroscopically viewed, in each of a case where thermal etching isperformed and a case where no thermal etching is performed.

FIG. 21 is a graph showing an exemplary relation between the channelmobility and an angle between a channel direction and a <0-11-2>direction.

FIG. 22 shows a modification of FIG. 15.

FIG. 23 is a partial cross sectional view schematically showing aconfiguration of a silicon carbide semiconductor device in a secondembodiment of the present invention.

FIG. 24 is a graph illustrating a relation between an impurityconcentration N_(A) of a lower drift layer and a breakdown voltage ineach of a case where a distance L_(A) is 3 μm, a case where distance LAis 5 μm, a case where distance LA is 10 μm, and a case where distance LAis 15 μm.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes embodiments of the present invention based onfigures. It should be noted that in the below-mentioned figures, thesame or corresponding portions are given the same reference charactersand are not described repeatedly. Regarding crystallographic indicationsin the present specification, an individual orientation is representedby [ ], a group orientation is represented by < >, and an individualplane is represented by ( ), and a group plane is represented by { }. Inaddition, a negative crystallographic index is normally expressed byputting “-” (bar) above a numeral, but is expressed by putting thenegative sign before the numeral in the present specification.

First, the following items (i) to (vii) provide the gist of theembodiments.

(i) Each of silicon carbide semiconductor devices 201, 202 includes afirst electrode 98, a first drift layer 81 a, a relaxation region 71, asecond drift layer 81 b, a body region 82, a source region 83, a secondelectrode 94, a gate insulating film 91, and a gate electrode 92. Firstdrift layer 81 a has a first surface P1 facing first electrode 98 andelectrically connected to first electrode 98 and a second surface P2opposite to first surface P1. First drift layer 81 a has firstconductivity type, and has an impurity concentration N_(A). Relaxationregion 71 is provided in a portion of second surface P2 of first driftlayer 81 a, and has a distance L_(A) from first surface P1. Relaxationregion 71 has second conductivity type. Second drift layer 81 b has athird surface P3 in contact with second surface P2, and a fourth surfaceP4 opposite to third surface P3. Second drift layer 81 b has the firstconductivity type. First drift layer 81 a and second drift layer 81 bform a drift region 81 in which relaxation region 71 is buried. Seconddrift layer 81 b has an impurity concentration N_(B), N_(B)>N_(A) beingsatisfied. Body region 82 is provided on fourth surface P4 of seconddrift layer 81 b. The body region has the second conductivity type.Source region 83 is provided on body region 82, and is separated fromthe drift region by body region 82. Source region 83 has the firstconductivity type. Second electrode 94 is electrically connected tosource region 83. Gate insulating film 91 includes a portion on bodyregion 82 to connect source region 83 and second drift layer 81 b toeach other. Gate electrode 92 is provided on gate insulating film 91.

According to each of silicon carbide semiconductor devices 201, 202,N_(B)>N_(A) is satisfied. Accordingly, when a voltage is applied betweenfirst electrode 98 and second electrode 94, a depletion layer is morefacilitated to expand from relaxation region 71 to first drift layer 81a as compared with extension of a depletion layer from body region 82 tosecond drift layer 81 b. Thus, a large ratio of the applied voltage isheld by first drift layer 81 a. Hence, electric field strength can besuppressed in second drift layer 81 b. Breakdown of the silicon carbidesemiconductor device is likely to occur in the second drift layer or astructure provided thereon. Hence, by suppressing electric fieldstrength in second drift layer 81 b as described above, the breakdownvoltage of each of silicon carbide semiconductor devices 201, 202 can beincreased.

Further, the impurity concentration of second drift layer 81 b is higherthan that in the case where N_(B)≦N_(A) is satisfied, so that electricresistance of second drift layer 81 b can be made low. This leads to asmall on-resistance of each of silicon carbide semiconductor devices201, 202.

As described above, there is obtained each of silicon carbidesemiconductor devices 201, 202 having a high breakdown voltage and a lowon-resistance.

(ii) Third surface P3 may have a distance L_(B) from fourth surface P4and L_(A)>L_(B) may be satisfied.

In this way, the ratio of voltage held by the first drift layer can bemore increased. Accordingly, the breakdown voltage can be moreincreased.

(iii) In item (ii) described above, L_(A)>2·L_(B) may be satisfied.

In this way, the ratio of voltage held by first drift layer 81 a can befurther increased. Accordingly, the breakdown voltage can be moreincreased.

(iv) L_(A)>5 μm may be satisfied.

Accordingly, a depletion layer having a length of 5 μm at maximum can beformed between relaxation region 71 and first surface P1. In otherwords, a depletion layer having a sufficient length can be formed moresecurely between relaxation region 71 and first surface P1. Therefore,the breakdown voltage of each of silicon carbide semiconductor devices201, 202 can be more increased.

(v) Relaxation region 71 may have a dose amount D_(R) andL_(A)·N_(A)<D_(R) may be satisfied. Here, the term “dose amount” isintended to mean an amount of impurity per unit area. The unit area is aunit area in a plane perpendicular to the thickness direction.

Accordingly, when each of silicon carbide semiconductor devices 201, 202is turned off to increase a voltage between first electrode 98 andsecond electrode 94, relaxation region 71 can be prevented from beingcompletely depleted before the depletion layer sufficiently extends fromrelaxation region 71 toward first surface P1. In this way, a depletionlayer having a sufficient length can be formed between relaxation region71 and first surface P1 in first drift layer 81 a. Accordingly, a largerratio of the voltage between first electrode 98 and second electrode 94is held by first drift layer 81 a. In other words, the voltage held bysecond drift layer 81 b is reduced. In this way, electric field strengthcan be further suppressed at the portion at which breakdown is likely tooccur due to concentrated electric fields. Accordingly, the breakdownvoltage of the silicon carbide semiconductor device is furtherincreased.

(vi) In silicon carbide semiconductor device 201, a trench TR may beprovided to have a side wall surface SW. Side wall surface SW extendsinto second drift layer 81 b through source region 83 and body region82. Further, side wall surface SW is separated from first drift layer 81a. Gate electrode 92 is disposed on side wall surface SW with gateinsulating film 91 being interposed therebetween.

In such a trench type silicon carbide semiconductor device, breakdown ofthe gate insulating film in the vicinity of an end portion of side wallsurface SW extending into the second drift layer is likely to be adetermination factor for breakdown voltage of the silicon carbidesemiconductor device. Even in such a case, with the feature of item (i)described above, a sufficient breakdown voltage can be secured whilesuppressing the on-resistance.

(vii) In silicon carbide semiconductor device 202, a flat surface PF maybe provided to have a portion constituted of each of source region 83P,body region 82P, and second drift layer 81 b and to be in parallel withfourth surface P4 of second drift layer 81 b. Gate electrode 92P isdisposed on flat surface PF with gate insulating film 91P beinginterposed therebetween.

In such a planar type silicon carbide semiconductor device 202,breakdown in the vicinity of an interface between second drift layer 81b and body region 82P is likely to be a determination factor forbreakdown voltage of silicon carbide semiconductor device 202. Even insuch a case, with the feature of item (i) described above, a sufficientbreakdown voltage can be secured while suppressing the on-resistance.

For more detailed description of the embodiments of the invention of thepresent application, the following illustrates first and secondembodiments and supplementary matters.

First Embodiment

As shown in FIG. 1 to FIG. 3, a MOSFET 201 (silicon carbidesemiconductor device) of the present embodiment includes asingle-crystal substrate 80, an epitaxial layer 101 (silicon carbidelayer), gate oxide films 91 (gate insulating film), gate electrodes 92,interlayer insulating films 93, source electrodes 94 (second electrode),a source interconnection layer 95, and a drain electrode 98 (firstelectrode). MOSFET 201 preferably has a breakdown voltage of not lessthan 600 V between drain electrode 98 and each source electrode 94. Inother words, MOSFET 201 is preferably a power semiconductor devicehaving a high breakdown voltage.

Single-crystal substrate 80 is made of silicon carbide and has n type(first conductivity type) conductivity. Single-crystal substrate 80 hasone surface (upper surface in the figure) on which epitaxial layer 101is provided, and has the other surface (lower surface in the figure) onwhich drain electrode 98 serving as an ohmic electrode is provided.Single-crystal substrate 80 preferably has a hexagonal crystal structureof polytype 4H.

Epitaxial layer 101 is a silicon carbide layer epitaxially grown onsingle-crystal substrate 80. Epitaxial layer 101 preferably has ahexagonal crystal structure of polytype 4H. Epitaxial layer 101 hasrelaxation regions 71, a drift region 81, body regions 82, sourceregions 83, and contact regions 84.

Drift region 81 has n type conductivity. Drift region 81 has a lowerdrift layer 81 a (first drift layer) and an upper drift layer 81 b(second drift layer). Lower drift layer 81 a has a first surface P1, anda second surface P2 opposite to first surface P1. First surface P1 facesdrain electrode 98, and is electrically connected to drain electrode 98via single-crystal substrate 80. Lower drift layer 81 a has n typeconductivity, and has an impurity concentration N_(A).

Relaxation regions 71 are formed in portions of second surface P2 oflower drift layer 81 a, and has a distance L_(A) from first surface P1.Preferably, L_(A)>5 μm is satisfied. Each of relaxation regions 71 has ptype (second conductivity type) conductivity, and contains an impurity,such as aluminum, added therein. Relaxation region 71 has a dose amountD_(R). Here, the term “dose amount” is intended to mean an amount ofimpurity per unit area. The unit area is a unit area in a planeperpendicular to the thickness direction (vertical direction in FIG. 1).In other words, the dose amount is a value obtained by integrating animpurity concentration per unit volume in the thickness direction.Preferably, L_(A)·N_(A)<D_(R) is satisfied. Relaxation region 71preferably has a dose amount of not less than 1×10¹² cm⁻², morepreferably, not less than 1×10¹³ cm⁻². This dose amount is preferablynot more than 1×10¹⁵ cm⁻². This dose amount is, for example, 3×10¹³cm⁻².

Upper drift layer 81 b is provided on second surface P2 of lower driftlayer 81 a. Upper drift layer 81 b has a third surface P3 in contactwith second surface P2, and a fourth surface P4 opposite to thirdsurface P3. Third surface P3 has a distance L_(B) from fourth surfaceP4. In other words, upper drift layer 81 b has a thickness L_(B).Distance L_(A) between relaxation region 71 and first surface P1 anddistance L_(B) between third surface P3 and fourth surface P4 preferablysatisfy L_(A)>L_(B), more preferably, L_(A)>2·L_(B). Lower drift layer81 a and upper drift layer 81 b form drift region 81 in which relaxationregions 71 are buried. In other words, upper drift layer 81 b coversrelaxation regions 71. Upper drift layer 81 b has n type conductivity,and has an impurity concentration N_(B).

Between impurity concentration N_(A) of lower drift layer 81 a andimpurity concentration N_(B) of upper drift layer 81 b, the followingrelation is satisfied: N_(B)>N_(A). Impurity concentration N_(A) ispreferably not less than 3×10¹⁵ cm⁻³ and not more than 1×10¹⁶ cm⁻³, forexample, 4×10¹⁵ cm⁻³. Impurity concentration N_(B) is preferably notless than 7×10¹⁵ cm⁻³ and not more than 5×10¹⁶ cm⁻³, for example,7.5×10¹⁵ cm⁻³. Single-crystal substrate 80 preferably has an impurityconcentration sufficiently larger than impurity concentration N_(A). Forexample, single-crystal substrate 80 has an impurity concentration 50times or more as large as impurity concentration N_(A). In such a case,single-crystal substrate 80 does not have a function as a drift region,i.e., does not substantially have a breakdown voltage holding function.

Each of body regions 82 is provided on fourth surface P4 of upper driftlayer 81 b. The body region has p type conductivity. Body region 82 isseparated from relaxation region 71 by upper drift layer 81 b. Bodyregion 82 preferably has an impurity concentration of not less than1×10¹⁷ cm⁻³ and not more than 5×10¹⁸ cm⁻³, such as 1×10¹⁸ cm⁻³.

Source region 83 is provided on body region 82, and is separated fromthe drift region by body region 82. The source region has n typeconductivity. Source region 83 and contact region 84 form the uppersurface of epitaxial layer 101. Contact region 84 has p typeconductivity. Contact region 84 is connected to body region 82.

In the MOSFET, a trench TR is provided in the upper surface of epitaxiallayer 101. Trench TR has side wall surfaces SW and a bottom surface BT.Each of side wall surfaces SW extends into upper drift layer 81 bthrough source region 83 and body region 82. Accordingly, side wallsurface SW includes a channel surface of MOSFET 201 on body region 82.Side wall surface SW is separated from lower drift layer 81 a. Bottomsurface BT is located in upper drift layer 81 b. In the presentembodiment, bottom surface BT has a flat shape substantially parallel tothe upper surface. Bottom surface BT and side wall surface SW areconnected to each other at a portion that forms a corner portion oftrench TR. In the present embodiment, trench TR extends to form a meshhaving a honeycomb structure when viewed in a plan view (FIG. 3). Inthis way, epitaxial layer 101 has its upper surface having a hexagonalshape surrounded by trench TR. Side wall surface SW is inclined relativeto the upper surface of epitaxial layer 101, and therefore expands in atapered manner toward the opening of trench TR. Side wall surface SWpreferably has a plane orientation inclined relative to the {0001} planeby not less than 50° and not more than 65°, more preferably, inclinedrelative to the (000-1) plane by not less than 50° and not more than65°. Preferably, side wall surface SW has a predetermined crystal plane(also referred to as “special plane”) particularly at a portion on bodyregion 82. Details of the special plane will be described later.

Preferably, when viewed in a plan view, relaxation region 71 is disposedonly external to bottom surface BT of trench TR as shown in FIG. 3. Inthe present embodiment, relaxation region 71 has an opening when viewedin a plan view. Specifically, relaxation region 71 has outer edge andopening substantially similar to the upper surface having the hexagonalshape.

Gate oxide film 91 covers each of side wall surfaces SW and bottomsurface BT of trench TR. Thus, gate oxide film 91 includes a portion onbody region 82 to connect source region 83 and upper drift layer 81 b toeach other. Gate electrode 92 is provided on gate oxide film 91. In thisway, gate electrode 92 has a portion disposed on side wall surface SWwith gate oxide film 91 being interposed therebetween.

Source electrode 94 is in contact with and therefore is electricallyconnected to each of source regions 83 and contact region 84. Sourceinterconnection layer 95 is in contact with source electrode 94. Sourceinterconnection layer 95 is, for example, an aluminum layer. Interlayerinsulating film 93 insulates between gate electrode 92 and sourceinterconnection layer 95.

According to the present embodiment, MOSFET 201 is provided with trenchTR having side wall surface SW. Side wall surface SW extends into upperdrift layer 81 b through source region 83 and body region 82, and isseparated from lower drift layer 81 a. Gate electrode 92 is disposed onside wall surface SW with gate oxide film 91 being interposedtherebetween. In such a trench type MOSFET 201, breakdown of gateinsulating film 91 in the vicinity of the end portion of side wallsurface SW extending into lower drift layer 81 b (corner portion oftrench TR) is likely to be a determination factor for the breakdownvoltage of MOSFET 201.

Here, N_(B)>N_(A) is satisfied between impurity concentration N_(A) oflower drift layer 81 a and impurity concentration N_(B) of upper driftlayer 81 b. Hence, when a voltage is applied between drain electrode 98and source electrode 94, a depletion layer is more facilitated to extendfrom relaxation region 71 to lower drift layer 81 a as compared withextension of a depletion layer from body region 82 to upper drift layer81 b. Thus, a large ratio of the applied voltage is held by lower driftlayer 81 a. Hence, electric field strength can be suppressed in upperdrift layer 81 b. As described above, the breakdown of MOSFET 201 islikely to occur at gate insulating film 91 on lower drift layer 81 b.Hence, by suppressing electric field strength in upper drift layer 81 b,the breakdown voltage of MOSFET 201 can be increased.

Further, the impurity concentration of upper drift layer 81 b is higherthan that in the case where N_(B)≦N_(A) is satisfied, so that electricresistance of upper drift layer 81 b can be made low. Accordingly, theon-resistance of MOSFET 201 can be made low.

As described above, there is obtained MOSFET 201 having a high breakdownvoltage and a low on-resistance.

When L_(A)>L_(B) is satisfied between distances L_(A) and L_(B) (FIG.1), in particular, when L_(A)>2·L_(B) is satisfied, the ratio of voltageheld by lower drift layer 81 a can be further increased. Accordingly,the breakdown voltage can be more increased.

When L_(A)>5 μm is satisfied, a depletion layer having a length of 5 μmat maximum can be formed between relaxation region 71 and first surfaceP1. In other words, a depletion layer having a sufficient length can beformed more securely between relaxation region 71 and first surface P1.Accordingly, the breakdown voltage of MOSFET 201 can be furtherincreased.

When L_(A)·N_(A)<D_(R) is satisfied and MOSFET 201 is turned off toincrease a voltage between drain electrode 98 and source electrode 94,relaxation region 71 can be prevented from being completely depletedbefore the depletion layer sufficiently extends from relaxation region71 toward first surface P1. Accordingly, a depletion layer having asufficient length can be formed between relaxation region 71 and firstsurface P1 in lower drift layer 81 a. Accordingly, a larger ratio ofvoltage between drain electrode 98 and source electrode 94 is held bylower drift layer 81 a. In other words, the voltage held by upper driftlayer 81 b is reduced. In this way, electric field strength can befurther suppressed at the portion at which breakdown is likely to occurdue to concentrated electric fields. Accordingly, the breakdown voltageof MOSFET 201 is further increased.

Further, lower drift layer 81 a and drain electrode 98 are electricallyconnected to each other via single-crystal substrate 80 having animpurity concentration higher than impurity concentration N_(A). Thus,the contact resistance of drain electrode 98 can be reduced.Accordingly, the electric resistance of drift region 81 can be increasedby the reduced contact resistance. Hence, the impurity concentration ofdrift region 81 can be further reduced. Therefore, the breakdown voltageof MOSFET 201 can be further increased.

When relaxation region 71 is disposed external to bottom surface BT oftrench TR when viewed in a plan view (FIG. 3) and MOSFET 201 is turnedoff, the depletion layer extends from relaxation region 71 to the cornerportion of trench TR at the edge of bottom surface BT of trench TR. Thisprovides further increased effect of the electric field relaxationstructure.

The following describes a method of manufacturing MOSFET 201 (FIG. 1).

As shown in FIG. 4, lower drift layer 81 a is formed on single-crystalsubstrate 80. Specifically, lower drift layer 81 a is formed throughepitaxial growth on single-crystal substrate 80. This epitaxial growthcan be achieved by employing a CVD (Chemical Vapor Deposition) methodthat utilizes a mixed gas of silane (SiH₄) and propane (C₃H₈) as amaterial gas and utilizes hydrogen gas (H₂) as a carrier gas, forexample. In doing so, it is preferable to introduce nitrogen (N) orphosphorus (P) as an impurity, for example.

As shown in FIG. 5, relaxation regions 71 having p type conductivity areformed in portions of second surface P2 of lower drift layer 81 a.Specifically, in second surface P2, acceptor ions (impurity ions forproviding second conductivity type) are implanted using an implantingmask (not shown).

As shown in FIG. 6, after relaxation regions 71 are formed, upper driftlayer 81 b having n type conductivity is formed on second surface P2.Accordingly, relaxation regions 71 are buried in drift region 81including lower drift layer 81 a and upper drift layer 81 b. Upper driftlayer 81 b can be formed using the same method as the method of forminglower drift layer 81 a.

As shown in FIG. 7, body region 82 and source region 83 are formed onfourth surface P4 of upper drift layer 81 b. As shown in FIG. 8, contactregions 84 are formed on body region 82. The formation of these can beperformed by, for example, ion implantation into the fourth surface ofupper drift layer 81 b (FIG. 6). In the ion implantation for formingbody region 82 and contact regions 84, ions of an impurity for providingp type conductivity such as aluminum (Al) are implanted. Meanwhile, inthe ion implantation for forming source region 83, ions of an impurityfor providing n type conductivity such as phosphorus (P) are implanted,for example. It should be noted that instead of the ion implantation,epitaxial growth involving addition of impurities may be employed.

Next, heat treatment is performed to activate the impurities. This heattreatment is preferably performed at a temperature of not less than1500° C. and not more than 1900° C., for example, a temperature ofapproximately 1700° C. The heat treatment is performed for approximately30 minutes, for example. The atmosphere in the heat treatment ispreferably an inert gas atmosphere, such as Ar atmosphere.

As shown in FIG. 9, a mask layer 40 having an opening is formed on thesurface provided by source region 83 and contact region 84. As masklayer 40, a silicon oxide film or the like can be used, for example. Theopening is formed to correspond to the location of trench TR (FIG. 1).

As shown in FIG. 10, in the opening of mask layer 40, source region 83,body region 82, and a portion of upper drift layer 81 b are removed byetching. An exemplary, usable etching method is reactive ion etching(RIE), in particular, inductively coupled plasma (ICP) RIE.Specifically, for example, ICP-RIE can be employed which uses SF₆ or amixed gas of SF₆ and O₂ as a reactive gas. By means of such etching, inthe region where trench TR (FIG. 1) is to be formed, a recess TQ isformed which has side walls each substantially perpendicular to theupper surface.

Next, thermal etching is performed in recess TQ. This thermal etchingcan be performed by, for example, heating in an atmosphere containing areactive gas having at least one or more types of halogen atom. The atleast one or more types of halogen atom include at least one of chlorine(Cl) atom and fluorine (F) atom. This atmosphere is, for example, Cl₂,BCL₃, SF₆, or CF₄. For example, the thermal etching is performed using amixed gas of chlorine gas and oxygen gas as a reactive gas, at a heattreatment temperature of, for example, not less than 700° C. and notmore than 1000° C.

It should be noted that the reactive gas may contain a carrier gas inaddition to the chlorine gas and the oxygen gas. As the carrier gas,nitrogen (N₂) gas, argon gas, helium gas, or the like can be used, forexample. When the heat treatment temperature is set at not less than700° C. and not more than 1000° C. as described above, a rate of etchingSiC is approximately, for example, 70 μm/hour. In addition, in thiscase, mask layer 40, which is formed of silicon oxide and therefore hasa very large selection ratio relative to SiC, is not substantiallyetched during the etching of SiC.

As shown in FIG. 11, by the above-described thermal etching, trench TRis formed in the upper surface of epitaxial layer 101. Preferably,during the formation of trench TR, the special plane is spontaneouslyformed on side wall surface SW, in particular, on body region layer 82.Next, mask layer 40 is removed by means of an appropriate method such asetching.

As shown in FIG. 12, gate oxide film 91 is formed to cover each of sidewall surfaces SW and bottom surface BT of trench TR. Gate oxide film 91can be formed by means of, for example, thermal oxidation. Thereafter,NO annealing may be performed using nitrogen monoxide (NO) gas as anatmospheric gas. A temperature profile has such a condition that thetemperature is not less than 1100° C. and not more than 1300° C. andholding time is approximately 1 hour, for example. Accordingly, nitrogenatoms are introduced in an interface region between gate oxide film 91and body region 82. As a result, formation of interface states in theinterface region is suppressed, thereby achieving improved channelmobility. It should be noted that a gas other than the NO gas may beemployed as the atmospheric gas as long as the nitrogen atoms can bethus introduced. After this NO annealing, Ar annealing may be furtherperformed using argon (Ar) as the atmospheric gas. The Ar annealing ispreferably performed at a heating temperature higher than the heatingtemperature in the above-described NO annealing and lower than themelting point of gate oxide film 91. This heating temperature is heldfor approximately 1 hour, for example. Accordingly, formation ofinterface states in the interface region between gate oxide film 91 andbody region 82 is further suppressed. It should be noted that instead ofthe Ar gas, another inert gas such as nitrogen gas may be employed asthe atmospheric gas.

As shown in FIG. 13, gate electrode 92 is formed on gate oxide film 91.Specifically, gate electrode 92 is formed on gate oxide film 91 so as tofill the region within trench TR with gate oxide film 91 interposedtherebetween. A method of forming gate electrode 92 can be performed by,for example, forming a film of conductor or doped silicon and performingCMP (Chemical Mechanical Polishing).

Referring to FIG. 14, interlayer insulating film 93 is formed on gateelectrode 92 and gate oxide film 91 so as to cover the exposed surfaceof gate electrode 92. Etching is performed to form openings ininterlayer insulating film 93 and gate oxide film 91. Through theopenings, each of source region 83 and contact region 84 is exposed onthe upper surface. Next, on the upper surface, source electrode 94 isformed in contact with each of source region 83 and contact region 84.Drain electrode 98 is formed on first surface P1, which is provided bydrift region 81, with single-crystal substrate 80 interposedtherebetween.

Referring to FIG. 1 again, source interconnection layer 95 is formed. Inthis way, MOSFET 201 is obtained.

(Special Plane)

Side wall surface SW described above has the special plane particularlyat its portion on body region 82. Side wall surface SW having thespecial plane includes a plane S1 having a plane orientation of {0-33-8}as shown in FIG. 15. In other words, on side wall surface SW of trenchTR, body region 82 is provided with a surface including plane S1. PlaneS1 preferably has a plane orientation of (0-33-8).

More preferably, side wall surface SW microscopically includes plane S1,and side wall surface SW microscopically further includes a plane S2having a plane orientation of {0-11-1}. Here, the term “microscopically”refers to “minutely to such an extent that at least the size about twiceas large as an interatomic spacing is considered”. As a method ofobserving such a microscopic structure, for example, a TEM (TransmissionElectron Microscope) can be used. Plane S2 preferably has a planeorientation of (0-11-1).

Preferably, plane S1 and plane S2 of side wall surface SW form acombined plane SR having a plane orientation of {0-11-2}. Specifically,combined plane SR is constructed of periodically repeated planes S1 andS2. Such a periodic structure can be observed by, for example, TEM orAFM (Atomic Force Microscopy). In this case, combined plane SR has anoff angle of 62° relative to the {000-1} plane, macroscopically. Here,the term “macroscopically” refers to “disregarding a fine structurehaving a size of approximately interatomic spacing”. For the measurementof such a macroscopic off angle, a method employing general X-raydiffraction can be used, for example. Preferably, combined plane SR hasa plane orientation of (0-11-2). In this case, combined plane SR has anoff angle of 62° relative to the (000-1) plane, macroscopically.

Preferably, in the channel surface, carriers flow in a channel directionCD (i.e., the thickness direction of the MOSFET (vertical direction inFIG. 1 or the like), in which the above-described periodic repetition isdone.

The following describes the detailed structure of combined plane SR.

Generally, regarding Si atoms (or C atoms), when viewing a siliconcarbide single crystal of polytype 4H from the (000-1) plane, atoms in alayer A (solid line in the figure), atoms in a layer B (broken line inthe figure) disposed therebelow, and atoms in a layer C (chain line inthe figure) disposed therebelow, and atoms in a layer B (not shown inthe figure) disposed therebelow are repeatedly provided as shown in FIG.16. In other words, with four layers ABCB being regarded as one period,a periodic stacking structure such as ABCBABCBABCB . . . is provided.

As shown in FIG. 17, in the (11-20) plane (cross section taken along aline XVII-XVII of FIG. 16), atoms in each of four layers ABCBconstituting the above-described one period are not aligned completelyalong the (0-11-2) plane. In FIG. 17, the (0-11-2) plane is illustratedto pass through the locations of the atoms in layers B. In this case, itis understood that each of atoms in layers A and C is deviated from the(0-11-2) plane. Hence, even when the macroscopic plane orientation ofthe surface of the silicon carbide single crystal, i.e., the planeorientation thereof with its atomic level structure being ignored islimited to (0-11-2), this surface can have various structuresmicroscopically.

As shown in FIG. 18, combined plane SR is constructed by alternatelyproviding planes S1 having a plane orientation of (0-33-8) and planes S2connected to planes S1 and having a plane orientation different fromthat of each of planes S1. Each of planes S1 and S2 has a length twiceas large as the interatomic spacing of the Si atoms (or C atoms). Itshould be noted that a plane with plane S1 and plane S2 being averagedcorresponds to the (0-11-2) plane (FIG. 17).

As shown in FIG. 19, when viewing combined plane SR from the (01-10)plane, the single-crystal structure has a portion periodically includinga structure (plane S1 portion) equivalent to a cubic structure.Specifically, combined plane SR is constructed by alternately providingplanes Si having a plane orientation of (001) in the above-describedstructure equivalent to the cubic structure and planes S2 connected toplanes S1 and having a plane orientation different from that of each ofplanes S1. Also in a polytype other than 4H, the surface can beconstructed of the planes (planes S1 in FIG. 24) having a planeorientation of (001) in the structure equivalent to the cubic structureand the planes (planes S2 in FIG. 16) connected to the foregoing planesand having a plane orientation different from that of each of theforegoing planes. The polytype may be, for example, 6H or 15R.

Referring to FIG. 20, the following describes a relation between thecrystal plane of side wall surface SW and mobility MB of the channelsurface. In the graph of FIG. 20, the horizontal axis represents anangle D1 formed by the (000-1) plane and the macroscopic planeorientation of side wall surface SW having the channel surface, whereasthe vertical axis represents mobility MB. A group of plots CM correspondto a case where side wall surface SW is finished to have the specialplane by thermal etching, whereas a group of plots MC correspond to acase where side wall SW is not thermally etched.

In group of plots MC, mobility MB is at maximum when the channel surfacehas a macroscopic plane orientation of (0-33-8). This is presumably dueto the following reason. That is, in the case where the thermal etchingis not performed, i.e., in the case where the microscopic structure ofthe channel surface is not particularly controlled, the macroscopicplane orientation thereof corresponds to (0-33-8), with the result thata ratio of the microscopic plane orientation of (0-33-8), i.e., theplane orientation of (0-33-8) in consideration of that in atomic levelbecomes statistically high.

On the other hand, mobility MB in group of plots CM is at maximum whenthe macroscopic plane orientation of the channel surface is (0-11-2)(arrow EX). This is presumably due to the following reason. That is, asshown in FIG. 18 and FIG. 19, the multiplicity of planes S1 each havinga plane orientation of (0-33-8) are densely and regularly arranged withplanes S2 interposed therebetween, whereby a ratio of the microscopicplane orientation of (0-33-8) becomes high in the channel surface.

It should be noted that mobility MB has orientation dependency oncombined plane SR. In a graph shown in FIG. 21, the horizontal axisrepresents an angle D2 between the channel direction and the <0-11-2>direction, whereas the vertical axis represents mobility MB (in anyunit) in the channel surface. A broken line is supplementarily providedtherein for viewability of the graph. From this graph, it has been foundthat in order to increase channel mobility MB, channel direction CD(FIG. 15) preferably has an angle D2 of not less than 0° and not morethan 60°, more preferably, substantially 0°.

As shown in FIG. 22, side wall surface SW may further include a plane S3in addition to combined plane SR. More specifically, side wall surfaceSW may include a combined plane SQ constructed of periodically repeatedplane S3 and combined plane SR. In this case, the off angle of side wallsurface SW relative to the {000-1} plane is deviated from the ideal offangle of combined plane SR, i.e., 62°. Preferably, this deviation issmall, preferably, in a range of ±10°. Examples of a surface included insuch an angle range include a surface having a macroscopic planeorientation of the {0-33-8} plane. More preferably, the off angle ofside wall surface SW relative to the (000-1) plane is deviated from theideal off angle of combined plane SR, i.e., 62°. Preferably, thisdeviation is small, preferably, in a range of ±10°. Examples of asurface included in such an angle range include a surface having amacroscopic plane orientation of the (0-33-8) plane.

Such a periodic structure can be observed by, for example, TEM or AFM.

Second Embodiment

As shown in FIG. 23, a MOSFET 202 of the present embodiment is of aso-called planar type. An epitaxial layer 102 includes body regions 82P,source regions 83P, and contact regions 84P. MOSFET 202 is provided witha flat surface PF. Flat surface PF has a portion constituted of each ofsource regions 83P, body regions 82P, and upper drift layer 81 b, and isin parallel with fourth surface P4 of upper drift layer 81 b. Gateelectrodes 92P are disposed on flat surface PF with gate oxide films 91Pbeing interposed therebetween. It should be noted that configurationsother than the above are substantially the same as those of the firstembodiment. Hence, the same or corresponding elements are given the samereference characters and are not described repeatedly.

In the present embodiment, breakdown in the vicinity of an interfacebetween lower drift layer 81 b and each body region 82P (in particular,corner portion CR) is likely to be a determination factor for breakdownvoltage of MOSFET 202. Even in such a case, due to substantially thesame reason as that in the first embodiment, a sufficient breakdownvoltage can be secured while suppressing the on-resistance.

(As to Relation Between Breakdown Voltage and Each of ImpurityConcentration N_(A) and Distance L_(d))

As shown in a simulation result of FIG. 24, when the impurity doseamount in the relaxation region is sufficiently high to such an extentthat relaxation region 71 is not completely depleted, the breakdownvoltage of the interface between relaxation region 71 and lower driftlayer 81 a is mainly determined by impurity concentration N_(A) of lowerdrift layer 81 a and distance L_(A) between relaxation region 71 andfirst surface P1. In a silicon semiconductor device, the upper limit ofsuch a breakdown voltage is approximately 600 V (see the broken line inthe figure). In the silicon carbide semiconductor device, when L_(A)≧5μm, a breakdown voltage of not less than 600 V was obtained.

Example 1

For MOSFET 201 (FIG. 1), by changing impurity concentrations N_(A),N_(B) and distances L_(A), L_(B), simulations 1 to 5 were performed withregard to the electric field strength and on-resistance R_(ON). Itshould be noted that simulation 1 corresponds to a comparative examplein which impurity concentrations N_(A) and N_(B) were equal to eachother. Results thereof are shown below.

TABLE 1 N_(A) L_(A) N_(B) L_(B) Efp/n Etrench Eox Epn Ron # [cm⁻³] [μm][cm⁻³] [μm] [MV/cm] [MV/cm] [MV/cm] [MV/cm] [mohm · cm²] 1 4.5 × 10¹⁵ 94.5 × 10¹⁵ 9 2.5 1.07 3.53 0.16 9.27 2 4.5 × 10¹⁵ 9 5.5 × 10¹⁵ 3 2.51.12 3.73 0.16 3.25 3 4.5 × 10¹⁵ 9 7.0 × 10¹⁵ 3 2.55 1.16 3.9 0.17 2.954 4.5 × 10¹⁵ 9 1.0 × 10¹⁶ 3 2.6 1.22 4.04 0.17 2.75 5 4.5 × 10¹⁵ 9 2.0 ×10¹⁶ 3 2.7 1.5 4.4 0.18 2.50

Here, “Efp/n” represents the maximum electric field strength in thevicinity of the interface between relaxation region 71 and lower driftlayer 81 a. “E_(trench)” represents the maximum electric field strengthin trench TR. “E_(OX)” represents the maximum electric field strength ingate oxide film 91. “Epn” represents the maximum electric field strengthin the vicinity of the interface between body region 82 and upper driftlayer 81 b.

Relaxation regions 71 provided in MOSFET 201 allows for effectivesuppression of E_(OX), but attention needs to be paid such that Efp/ndoes not become too high. In simulation 1 (Comparative Example) andsimulation 2 (Example), Efp/n was suppressed to approximately the samedegree. On the other hand, on-resistance R_(ON) was suppressed more inthe latter (Example). As indicated by simulations 3 to 5, by increasingimpurity concentration N_(B), on-resistance R_(ON) is furthersuppressed.

Example 2

For MOSFET 202 (FIG. 23), simulations similar to those above wereperformed. Results thereof are shown below.

TABLE 2 N_(A) L_(A) N_(B) L_(B) Efp/n Epn Ron # [cm⁻³] [μm] [cm⁻³] [μm][MV/cm] [MV/cm] [mohm · cm²] 1 4.5 × 10¹⁵ 9 4.5 × 10¹⁵ 9 1.67 1.28 7.662 4.5 × 10¹⁵ 9 7.0 × 10¹⁵ 3 1.98 1.32 4.06

On resistance R_(ON) in simulation 2 (Example) is suppressed as comparedwith on-resistance R_(ON) in simulation 1 (Comparative Example).

The embodiments and examples disclosed herein are illustrative andnon-restrictive in any respect. The scope of the present invention isdefined by the terms of the claims, rather than the embodimentsdescribed above, and is intended to include any modifications within thescope and meaning equivalent to the terms of the claims. For example,the trench is not limited to the trench having the flat bottom surface,and may have a U-shaped or V-shaped cross sectional shape. Further, thesilicon carbide semiconductor device is not limited to the MOSFET, andmay be an IGBT (Insulated Gate Bipolar Transistor), for example. In thiscase, the above-described source electrode, source region, and drainelectrode respectively have functions as an emitter electrode, anemitter region, and a collector electrode. Moreover, in each of theabove-described embodiments, the first conductivity type is n type, andthe second conductivity type is p type, but these conductivity types maybe replaced with each other. In this case, the donor and the acceptor inthe above description are also replaced with each other. It should benoted that in order to attain higher channel mobility, the firstconductivity type is preferably n type. Further, the silicon carbidesemiconductor device does not need to have the single-crystal substrate,and may have no single-crystal substrate.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the scopeof the present invention being interpreted by the terms of the appendedclaims.

What is claimed is:
 1. A silicon carbide semiconductor devicecomprising: a first electrode; a first drift layer that has a firstsurface facing said first electrode and electrically connected to saidfirst electrode and a second surface opposite to said first surface,that has first conductivity type, and that has an impurity concentrationN_(A); a relaxation region that is provided in a portion of said secondsurface of said first drift layer, that has a distance L_(A) from saidfirst surface, and that has second conductivity type; a second driftlayer that has a third surface in contact with said second surface and afourth surface opposite to said third surface, and that has said firstconductivity type, said first drift layer and said second drift layerforming a drift region in which said relaxation region is buried, saidsecond drift layer having an impurity concentration N_(B), N_(B)>N_(A)being satisfied; a body region that is provided on said fourth surfaceof said second drift layer and that has said second conductivity type; asource region that is provided on said body region, that is separatedfrom said drift region by said body region, and that has said firstconductivity type; a second electrode electrically connected to saidsource region; a gate insulating film including a portion on said bodyregion to connect said source region and said second drift layer to eachother; and a gate electrode provided on said gate insulating film, atrench being provided to have a side wall surface extending into saidsecond drift layer through said source region and said body region andseparated from said first drift layer, a gate insulating film beingformed to cover the side wall surface and a bottom surface of saidtrench.
 2. The silicon carbide semiconductor device according to claim1, wherein said third surface has a distance L_(B) from said fourthsurface and L_(A)>L_(B) is satisfied.
 3. The silicon carbidesemiconductor device according to claim 2, wherein L_(A)>2·L_(B) issatisfied.
 4. The silicon carbide semiconductor device according toclaim 1, wherein L_(A)>5 μm is satisfied.
 5. The silicon carbidesemiconductor device according to claim 1, wherein said relaxationregion has a dose amount D_(R) and L_(A)·N_(A)<D_(R) is satisfied. 6.The silicon carbide semiconductor device according to claim 1, whereinsaid gate electrode is disposed on said wall surface with said gateinsulating film being interposed therebetween.
 7. The silicon carbidesemiconductor device according to claim 1, wherein a silicon carbidelayer including said first drift layer, said relaxation region, saidsecond drift layer, said body region and said source region has an uppersurface having a hexagonal shape surrounded by said trench, and saidrelaxation region has outer edge and opening substantially similar tosaid upper surface having the hexagonal shape.
 8. The silicon carbidesemiconductor device according to claim 1, wherein said side wallsurface of said trench includes a plane having a plane orientation of{0-33-8}.
 9. A silicon carbide semiconductor device comprising: a firstelectrode; a first drift layer that has a first surface facing saidfirst electrode and electrically connected to said first electrode and asecond surface opposite to said first surface, that has firstconductivity type, and that has an impurity concentration N_(A); arelaxation region that is provided in a portion of said second surfaceof said first drift layer, that has a distance L_(A) from said firstsurface, and that has second conductivity type; a second drift layerthat has a third surface in contact with said second surface and afourth surface opposite to said third surface, and that has said firstconductivity type, said first drift layer and said second drift layerforming a drift region in which said relaxation region is buried, saidsecond drift layer having an impurity concentration N_(B), N_(B)>N_(A)being satisfied; a body region that is provided on said fourth surfaceof said second drift layer and that has said second conductivity type; asource region that is provided on said body region, that is separatedfrom said drift region by said body region, and that has said firstconductivity type; a second electrode electrically connected to saidsource region; a gate insulating film including a portion on said bodyregion to connect said source region and said second drift layer to eachother; and a gate electrode provided on said gate insulating film, aflat surface being provided to have a portion constituted of each ofsaid source region, said body region, and said second drift layer and tobe in parallel with said fourth surface of said second drift layer, saidgate electrode being disposed on said flat surface with said gateinsulating film being interposed therebetween.